Pipelined Multi-core MIPS Machine - Kovalev, Mikhail a Muller, Silvia M. a Paul, Wolfgang J.

It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory.